PowerVR Series9XM Graphic Processor
The PowerVR Series9XM family features include: an scalable compute cluster architecture; high efficiency compression technology i…
- GPU
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
PowerVR Series9XM Graphic Processor
The PowerVR Series9XM family features include: an scalable compute cluster architecture; high efficiency compression technology i…
PowerVR Series9XE Graphic Processor
The PowerVR Series9XE family features include: an scalable compute cluster architecture; high efficiency compression technology i…
AMBA AHB 4 Channel DMA Controller
The AHB 4 Channel DMA Controller is a multiple-channel direct memory access controller.
AHB Single Channel DMA Controller
The DMA is a configurable single channel direct memory access controller.
AHB Quad SPI Controller with Execute in Place (XIP)
The Quad Serial Peripheral Interface module either controls a serial data link as a master component, or reacts to a serial data …
The SPI to AHB Lite Bridge IP core is commonly used as a monitor interface to allow external devices to access the internal AHB b…
APB Channel with Decoder and Data Mux
The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master.
AHB Channel with Decoder and Data Mux IP Core
The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master.
The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters.
AXI External Memory Controller
The AXI External Bus Interface (EBI) allows the processor to transmit and receive data to an external device, usually a memory (S…
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction.
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Mast…
Neural Network Acceleration for Automotive AI
State-of-the-art NPU for automotive inference, with many features built-in to maximize performance for a wide range of automotive AI applications.
IP
IP
USB2.0 PHY - SMIC 110nm generic
IP
12 Bit ADC - SMIC 110nm generic
IP
IP
Power regulator - SMIC 110nm generic
IP