Vendor: Silvaco, Inc. Category: Protocol Bridge

AXI to APB Bus Bridge

The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction.

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Overview

The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one governing the AXI transactions, and one governing APB transactions.

The AXI to APB Bridge acts as an AXI Slave component, and an APB Master component in an AXI/APB subsystem. Typically, the AXI to APB Bridge has its AXI interface connected to a Slave component port on an AXI Channel/Interconnect module, and its APB interface connected to the Master component port on an APB Channel module.

Key features

  • Translates AMBA® AXI transactions to APB transactions
  • Low latency
  • Low Gate Count
  • Supports APB 2.0 and APB 3.0 Signaling
  • Independent ACLK, PCLK pseudo-synchronous clocks

Block Diagram

AXI to APB Bus Bridge block diagram

What’s Included?

  • Verilog Source
  • Complete Test Environment
  • AHB Bus Functional Model

Specifications

Identity

Part Number
AXI to APB Bus Bridge
Vendor
Silvaco, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Silvaco, Inc.
HQ: United States
Contact Silvaco, Inc.

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Frequently asked questions about Protocol Bridge IP cores

What is AXI to APB Bus Bridge?

AXI to APB Bus Bridge is a Protocol Bridge IP core from Silvaco, Inc. listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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