PowerVR Neural Network Accelerator
The Series3NX-F brings programmable extensibility to the Series3NX architecture.
- NPU
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
PowerVR Neural Network Accelerator
The Series3NX-F brings programmable extensibility to the Series3NX architecture.
High-performance IP for graphics, AI/ML, and automotive products
16 state DVB-RCS2 Turbo Encoder
This is a 16 state DVB-RCS2 compatible parallel concatenated turbo encoder.
eNOR embedded Flash embedded IP
Zhuhai Chuangfeixin’s Floating-gate eNOR Flash memory macro are silicon characterized and qualified on Huali Microelectronics Cor…
Time Synchronization over Internet Protocol
The ST 2059 core is an FPGA IP core that generates timing and clock signals according to the SMPTE ST 2059 standard defined by th…
The TRC16024CPA is a four lane Gen 1,2,3,4 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transm…
AI and DSP performance leader with up to 4X the NN performance and 2X the DSP performance of the HiFi 4 DSP, ideal for digital as…
Entry-level network-on-chip (NoC) IP for low power and cost efficiency.
5V I/O and ESD in TSMC 12nm FFC/FFC+
A 5V Library for Generic I/O and ESD Applications TSMC 12NM FFC/FFC+ process.
USB 1.1 Device Controller IP is based on the latest USB 1.1 specification from USB Implementer Forum (USB-IF) and is compatible w…
USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
Our company offers a configurable and adaptable USB 2.0 OTG controller IP core, suitable for a wide range of applications.
OTP One Time Programmable IP SIL180
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/4…
OTP One Time Programmable IP SIL130HV
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/4…
OTP One Time Programmable IP SMIC130
Chuangfeixin (CFX)'s OTP IP is adopted in different generations of logic and HV technology (0.18/0.16/0.13/0.11 um and 90/65/55/4…
First High Performance Split-Lock DynamIQ CPU
The all new Arm Cortex-A family of Automotive Enhanced (AE) high performance processors is designed for devices undertaking compl…
180nm MTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's TwinBit(TM) is the only embedded CMOS, multi-time programmable (MTP), non-volatile RAM IP of its kind, utilizing the 'ho…
The I2C library provides open-drain bi-directional I/O cells designed for the I2C two-line interface.
The CML library provides a differential current mode logic clock driver to support REFCLK signaling in PCIe applications along wi…
1.8V Programmable 100MHz Oscillator Staggered I/O Pad Set
The 1.8V 100MHz Oscillators library includes a programmable oscillator macro I/O cell.
The LPDDR2/3_DDR3/4 libraries contain the 7-way combo driver/receiver cells with embedded power cells, the driver impedance calib…