Vendor: Cadence Design Systems, Inc. Category: GDDR

GDDR6 PHY and Controller

High-performance IP for graphics, AI/ML, and automotive products

Controller + 1 View all specifications

Overview

Cadence silicon-proven GDDR6 PHY and controller IP showcase leading-edge BER, BIST, and RAS capabilities. GDDR6 offers significantly more performance than the fastest speed of DDR5 at a moderate cost, making it ideal for high-bandwidth applications. Cadence’s unique, single-vendor GDDR6 IP solution speeds up integration and reduces interoperability risk.

Key features

PHY

  • Single configuration supports one GDDR6 device per channel (coplanar) or two GDDR6 devices per channel (clamshell)
  •  DFI PHY Independent Mode for initialization and training
  • Adaptive and continuous timing recovery
  •  Internal and external datapath loop-back modes
  •  Transmit crosstalk cancelation of immediate neighbors
  •  Per-bit DFE, CTLE, and FFE equalization

Controller

  • In-line SEC/DED ECC
  • Supports advanced RAS features including error scrubbing, parity, etc.
  • Compatible with GDDR6 devices compliant to JESD250b
  • Single and multi-port host options for Arm® AMBA®4, AMBA 3 AXI, and low-latency Denali interfaces
  • QoS features allow command prioritization
  • Flexible paging policy
  • Memory controller interface is based on DFI 5.0
  • The controller runs at 1/8 of the memory clock speed for ease of timing closure

Block Diagram

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Benefits

  • Proven: Silicon characterization reports available in multiple process technologies and foundries
  • Low Latency: For data-intensive applications
  • Low Power and Area: Industry-leading PPA based on advanced architecture and implementation
  • Low BER: Supporting standard PCB materials
  • Reliable: Maximum system margin with advanced clocking and I/O architectures
  • Future proof: Cutting edge technology with the latest GDDR protocols and the highest data rates

Specifications

Identity

Part Number
GDDR6 PHY and Controller
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
Controller , PHY

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about GDDR IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about GDDR Interface IP

What is GDDR6 PHY and Controller?

GDDR6 PHY and Controller is a GDDR IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this GDDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GDDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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