CXL Host Device Dual mode controllers
Primesoc's CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.
- CXL
- Matured- FPGA validated
- Immediate
- CXL Spec V1.1
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
CXL Host Device Dual mode controllers
Primesoc's CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.
Adaptive Body Bias Generator - GLOBALFOUNDRIES 22FDX
RI_ABB_GF22FDX is a cutting-edge adaptive body bias (ABB) generator for GLOBALFOUNDRIES® 22FDX® technology.
The USB 2.0 Hub IP core provides a link between the USB2.0 Host and multiple USB peripherals via UTMI + Low pin interface (ULPI).
Super Speed USB 3.0 Extensible Host Controller xHCI
USB3.0 Super-Speed Host The Super-Speed USB Host Controller is designed for flexibility, ease of use and provides ASIC/FPGA desig…
9 track Near Threshold Voltage standard cell library at TSMC 55 nm
TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing…
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as s…
SATA Port Multiplier with Sandbox
The IntelliProp IPP-SA128A-PM (SATA Port Multiplier with Sandbox) device is an IP core that provides SATA Port Multiplier functio…
Dolphin Technology provides Triple Timer Counter (TTC) IP with three independent timer/counter modules that can each be clocked u…
High-performance 32-bit processor for real-time control
R807 utilizes an 8-stage pipeline and dual-issue out-of-order architecture.
AIoT processor with vector computing engine
I805 utilizes a 4-stage sequential pipeline, and is equipped with a vector computing engine oriented to applications such as AI a…
Low power 32-bit processor with lightweight computing power
E804 utilizes a 3 to 4-stage variable-length pipeline and a scalar DSP computing engine, and can be optionally equipped with a fl…
Ultra-low power 32-bit processor resistant to physical damage
S802 utilizes a 2-stage minimalistic pipeline that provides nearly 20 special protection technologies for various invasive and no…
UDP/IP – 1 GbE Protocol Hardware Stack
The DB-UDP-IP-1GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 1 GbE…
UDP/IP – 10 GbE Protocol Hardware Stack
The DB-UDP-IP-10GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 10 G…
UDP/IP – 25 GbE Protocol Hardware Stack
The DB-UDP-IP-25GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 25 G…
UDP/IP – 40 GbE Protocol Hardware Stack
The DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 40 &…
UDP/IP – 50 GbE Protocol Hardware Stack
The DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 50 G…
Ultra-low power processor with RISC-V architecture possessing secure execution capability
E902 utilizes a 2-stage minimalistic pipeline compatible with RISC-V architecture, and is enhanced in execution efficiency.
Scalable Ultra-High Throughput Lossy and Lossless JPEG 2000 Encoder
The UHT-JPEG2K-E core is a scalable, ultra-high throughput, hardware JPEG 2000 encoder, designed to provide all the power needed …
10M/100M/1G/10G/25G Unmanaged Ethernet Switch
Silicon-Agnostic, Compact and flexible Ethernet Switch IPs Unmanaged Ethernet Switch IP cores are a family of Ethernet switching …