32x1 Bits OTP (One-Time Programmable) IP, MXIC 0.18um 1.8V/5V Logic Process
The ATO00032X1MX180LB52NC is organized as a 32-bit by 1 one-time programmable (OTP).
- eFuse / OTP
- Silicon Proven & Ready for Production
- Now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
32x1 Bits OTP (One-Time Programmable) IP, MXIC 0.18um 1.8V/5V Logic Process
The ATO00032X1MX180LB52NC is organized as a 32-bit by 1 one-time programmable (OTP).
64x8 Bits OTP (One-Time Programmable) IP, Nexchip 0.15um 3.3V Logic Processes
The ATO00064X8NX150FPS3NA is organized as a 64x8 one-time programmable (OTP).
32x1 Bits OTP (One-Time Programmable) IP, MXIC 0.18um 1.8V/5V Logic 18A Process
The ATO00032X1MX180LOG2NA is organized as a 32-bit by 1 one-time programmable (OTP).
512x16 Bits OTP (One-Time Programmable) IP, DB HiTek AN180 1.8V / 5V Process
The ATO0512X16DB180AO14NA is organized as 512x16 One-Time Programmable in 16-bit read and 1-bit program modes.
SiliconIntervention applies an architectural approach to solving the real-world problem of maximizing efficiency in Class-D drive…
IP
Active Programmable Low Pass Filter
The WEA321250LPF25CH5ST55 is an active 5th order Chebyshev Low Pass filter, synthesized in a Leapfrog architecture.
Synopsys 3DIO IP Solution is a specialized IO for multi-die integration.
Fully compliant solution that provides Ethernet Layer 2 Security for port and data privacy The MAC Privacy Protection IP is a ful…
The NTN System Test Bench (STB) is a cost-effective, flexible environment for NTN satellite network operators or applications dev…
PCIe 7.0 Switch with with Time Division Multiplexing
The PCI Express® (PCIe®) 7.0 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementati…
PCIe 7.0 Retimer Controller with CXL Support
PCI Express® (PCIe®) 7.0 links operating at 128 GT/s using PAM4 signaling have a reach of up to 13 inches at nominal conditions o…
The PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations.
The PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations.
Octa-core LPU IP on LISA v3 — multi-chip scalable, purpose-built for multimodal, agentic AI at the edge and on-prem.
LPDDR4X/4 & LPDDR5T/5X/5 Combo Controller
The LPDDR4 and LPDDR5 combo controller core is designed for use in applications requiring high memory throughput at low power inc…
Post Quantum ready Public Key Crypto HW acceleration library optimized for networking applications
eSi-PQC-HT is a post quantum ready Public Key Crypto HW acceleration library, optimized for networking applications.
LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithm…
Centralised Real Time Processor IP Core
We provide many configurations for our cryptographic solutions based on the requirements of the project.
DDR5 REGISTERING CLOCK DRIVER (RCD) IP - (DDR5RCD03)
The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs.