CAST IP Listing

Configurable automotive Peripheral Sensor Interface (PSI5) host controller that implements the ECU side of PSI5 communication systems

• SENT

This PDM2PCM is a configurable audio interface core that converts a mono or stereo Pulse Density Modulation (PDM) stream into sta…

• PDM

Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection.

• Ethernet

The TSN-EP-10G implements a configurable controller meant to ease the implementation of endpoints for networks complying with the…

• Ethernet

The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external…

• IEEE-1588 / PTP

The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard.

• Image Conversion

The KiviPQC™-Box is a hardware accelerator for post-quantum cryptographic operations.

• CRYSTALS-Dilithium (ML-DSA)

The KiviPQC™-DSA is a hardware accelerator for post-quantum cryptographic operations.

• CRYSTALS-Dilithium (ML-DSA)

The AC97-CTRL Audio Controller is a configurable IP block designed to simplify the integration of the AC'97 audio interface into …

• AC'97

LZ4SNP-C is a custom hardware implementation of a lossless data compression engine that complies with the LZ4 and Snappy compress…

• Data Compression

The MC-SDMA IP core implements a configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that tr…

• DMA

The CSENT-TX core implements a transmitter for the Single Edge Nibble Transmission (SENT) protocol.

• SENT

The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol.

• SENT

The KiviPQC™-KEM is a hardware accelerator for post-quantum cryptographic operations.

• CRYSTALS-Kyber (ML-KEM)

The SNOW-V IP core implements the SNOW-V stream cipher mechanism, aiming to meet the security demands of modern high-speed commun…

• Symmetric Crypto

GEON-SoC is an area-efficient, processor-agnostic, hardware root of trust for SoC designs.

• Root Of Trust

The SPI2AHB core implements an SPI slave to AHB-Lite master bridge.

• SPI / QSPI XSPI

Implements a controller for a single-, dual-, quad-, or octal-lane Serial Peripheral Interface (SPI) bus, which can operate eithe…

• SPI / QSPI XSPI

The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C …

• I2C / I3C

The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus.

• Protocol Bridge