The logiSPI SPI to AXI4 Controller Bridge IP core from Xylon's logicBRICKS IP library enables easy inter-chip board-level interfa…
- SPI / QSPI XSPI
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The logiSPI SPI to AXI4 Controller Bridge IP core from Xylon's logicBRICKS IP library enables easy inter-chip board-level interfa…
Complete FEC Encoder Solution compliant to LTE/ LTE A Specification
The Lekha IP – 3GPP LTE FEC Encoder IP Core V1.0 addresses the implementation of the FEC building blocks compliant to 3GPP TS 36.…
ITU-T G729A Voice Codec Hardware Accelerator
The growth in wireless communication systems, cellular mobile radio and VoIP technology has created the imperative need for bandw…
Jointwave's AVC Untra Codec just needs very low resource on both FPGA & ASIC.
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps.
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream.
Mobile Phase Recovering Equalizer
The Mobile Phase Recovering Equalizer (MPRE) FPGA core combines Channel Equalization, Phase Recovery, and Symbol Slicing in a sin…
Universal NVM Express Controller (UNEX)
The Universal NVM Express Controller (UNEX) is flexible and configurable design targeted for both Enterprise and client class sol…
The RapidlO-AXI Bridge (RIO-AXI Bridge) is a flexible and configurable IP used along with the native RapidlO Controller (GRIO) to…
The 10/100/1000Mbps Tri-mode Ethernet MAC offers an IEEE802.3-2008 compliant solution that meets the requirements for tri-mode LA…
Certified USB 5G & 10G Dual Mode Controller
USB 5G, 10G Dual Mode controller is a configurable core and implements the USB Host functionality or USB Device functionality sel…
I2C Controller IP – Master, Parameterized FIFO, AXI Bus
The DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP – Master, Parameterized FIFO, AHB Bus
The DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2…
I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mo…
I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
The DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…
I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
The DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AMBA AXI Bus to an I2C Bus in Standard-Mode (100 Kbit/s)…
16/32-bit Microprocessor with BDM
The D68000-BDM soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor.
Advanced Flash Controller Interface Core
The IPC-BL157A-ZM, Flash Controller Interface (AFCI) is a register level interface that allows software and hardware state machin…
10/100 Mb Media Access Controller with RMII
Our solution is a hardware implementation of media access control protocol defined by the IEEE standard.
High Performance Second Generation Extended MIPI CSI2 Receiver
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps.