SPI to AXI4 Controller Bridge

The logiSPI SPI to AXI4 Controller Bridge IP core allows external host processors to communicate with peripherals or processors implemented in Xilinx Zynq-7000 All Programmable SoC and FPGAs through the Serial Peripheral Interface (SPI) serial bus. In enables easy implementations of Xilinx FPGA/SoC companion chips that expand the capabilities of the embedded host processor by adding missing host features and by offloading high-speed processing tasks. The IP core works as a SPI Slave bus controller and a 32-bit master controller on the AMBA Advanced eXtensible Interface (AXI4) on-chip bus.

The SPI is a full-duplex synchronous and a four-wire serial interface between a single bus master, and one or more bus slave devices. The bus master initiates communication by asserting slave’s select signal and issuing a data frame (SPI telegram). Data is exchanged between the master and the selected slave device shift registers, which shift data bits synchronous on SPI clock signal generated by the master device.

The logiSPI IP core accepts the SPI telegram sent by the SPI master, de-serializes it, decodes SPI Master’s commands and writes/reads data to/from Xilinx Zynq-7000 SoC or FPGA peripherals and on-chip memories interconnected with a high-speed 32-bit AXI4 on-chip bus. By mean of SoC/FPGA memory controllers, the logiSPI can relay large bursts of data (up to 2 kBytes) between the SPI master device and SDRAM-type memories connected to the Xilinx Zynq-7000 SoC or FPGA device.

The logiSPI SPI to AXI4 Controller Bridge IP core implements an acknowledgment mechanism that assures integrity of data exchanged through the SPI bus. Properly decoded SPI telegrams are acknowledged by the command code bounced back to the SPI master, and the faulty telegrams are discarded. By asserting and deasserting the slave select signal, the SPI master can reset the logiSPI IP core’s operation.

• Supports Xilinx® Zynq®-7000 All Programmable SoC and all Xilinx FPGA families
• Bridge controller between the Serial Peripheral Interface (SPI) bus and the Advanced eXtensible Interface (AXI4) on-chip bus
• Works as a Slave controller on the SPI bus, and a master controller on the ARM® AMBA® AXI4 bus
• Enables full-duplex communication (MSB first) between an external SPI Master controller and SoC/FPGA peripherals, on-chip and off-chip memories
• Supports SPI telegrams of different lengths: single transfers or burst transfers (up to 2 kB, back-to-back)
• Supports four signals interface (SI, SO, SCLK and SCS_N)
• Provides transfer status signals, SPI telegrams acknowledgment and Slave reset mechanisms
• Supports SCLK frequency of up to fclk/4, where fclk is frequency of the system clock (AXI4 clock)
• Supports all SPI clock polarity (CPOL) and phase (CPHA) combinations
• Prepared for Xilinx Vivado® and ISE® Design Suits

• Easy control Xilinx FPGA and Zynq-7000 SoC implemented co-processors by virtually any microcontroller (MCU)

• Inter-chip board-level communications; i.e. external MCU controlling FPGA co-processor

• encrypted VHDL source