Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Scalable Ultra-High Throughput 8/10/12-bit JPEG Decoder
The UHT-JPEG-D core is a scalable, ultra-high throughput, 8-bit Baseline and 10/12-bit Extended hardware JPEG decoder, designed t…
Scalable Ultra-High Throughput 8/10/12-bit JPEG Encoder with Video Rate Control
The UHT-JPEG-E core is a scalable, ultra-high throughput, 8-bit Baseline and 10/12-bit Extended hardware JPEG encoder, with optio…
AES Encryption & Decryption IP Core − Programmable Block Cipher Modes
The AES-P IP core implements the FIPS-197 Encryption Standard.
SHA-3, SHA-2, SHA-1, SM3, MD5, Hash Accelerators
The HASH-IP-57 (EIP-57) is IP for accelerating the various secure hash integrity algorithms like MD5 (RFC1231), SHA-1 (FIPS-180-2…
The Kasumi-IP-06 (EIP-06) cipher accelerators implement the specification of the 3GPP Confidentiality and Integrity Algorithms as…
SHA-1, SHA-2, SHA-3 Hash based HMAC, accelerators
HMAC-IP-59 (EIP-59) is IP for accelerating the various single pass HMAC (FIPS-198-1) algorithms using secure hash integrity algor…
Flexible and Silicon proven Ethernet Layer 2 Security solution The MACsec IP provides Ethernet Layer 2 Security for port authenti…
Aurora-like 8b/10b @3Gbps for ALTERA Devices
REFLEX CES introduces the industry’s first release of its Aurora-‐like IP Core based on ALTERA FPGA enabling interoperability be…
BAYER_TO_RGB is a fully pipelined Bayer-mapped to RGB converter IP Core.
High Speed Low Power JPEG Codec IP Core
High Speed Low Power JPEG Codec IP Core
The VMESmodule is a VME Slave Controller core bridging the VME bus and the local bus.
Extensible Framework (EFW) For Xilinx KC705 Module
Extensible FPGA Framework (EFW) provides a verified set of productivity solutions, including module targeted physical interface c…
The USB 2.0 Host Controller IP Core is a 32-bit Avalon/AXI/AHB interface compliant core and supports ULPI interface.
USB 2.0 Device with FIFO Interface (USB20HF)
USB 2.0 device, FIFO interface (USB20HF) IP Core provides FIFO interface for endpoints and ULPI interface for Host communication.
The SD/eMMC Host Controller IP Core implements the SD Physical Layer v3.0 and eMMC Physical Layer v4.51 compatible Host Controlle…
Floating-point to Fixed-point Converter
Converts 32-bit floating-point numbers to fixed-point representation.
Fixed-point to 32-bit floating-point converter
FIXED_TO_IEEE is a high-speed fully pipelined conversion unit that accepts a signed fixed-point number as input and generates a 3…
32-bit Floating-point Divider IP Core
High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard.
High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard.
High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard.