256x8 Bits OTP (One-Time Programmable) IP, TSMC 40G 0.9/1.8V Process
The AT256X8T40G6AA is organized as 256 bits by 8 one-time programmable (OTP).
- TSMC
- 40nm
- G
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
256x8 Bits OTP (One-Time Programmable) IP, TSMC 40G 0.9/1.8V Process
The AT256X8T40G6AA is organized as 256 bits by 8 one-time programmable (OTP).
256x8 Bits OTP (One-Time Programmable) IP, TSMC 22ULP 0.8V/1.8V process
The AT256X8T22ULP6AA is organized as 256 bits by 8 one-time programmable (OTP).
4Kx32 Bits OTP (One-Time Programmable) IP, TSMC 40nm ULP 1.1V/2.5V Process
The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP).
1x64 Bits OTP (One-Time Programmable) IP, TSMC 0.18um Mixed-Signal 1.8V/3.3V Process
The AT1X64T180MM0AB is organized as one by 64 bits one-time programmable (OTP).
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
The Ceva-PentaG2 is a IP platform for implementing a wide range of user-equipment and IoT cellular modems.
High Speed Access & Test IP USB Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle.
High Speed Access & Test IP PCIE Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle.
CYB-RS-en core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
CYB-RS-de core implements the Reed Solomon decoding algorithm and is parameterized in terms of bits per symbol, maximum codeword …
The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification.
The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
SHA256 is a Secure Hash Algorithms which is one of the latest hash functions standarized by the U.S Federal Government.
Voltage/Current References - 1.21V ±0.5%, 600nA ±10% - GlobalFoundries 0.13µm Lite
This macro-cell is a low power voltage-current reference (1.21V / 600nA) with high accuracy (±0.5% over PVT) after trimming.
IEEE 802.15.4 Wireless Baseband IP
The LP-802.15.4 is a power and area-optimized implementation of the IEEE 802.15.4 physical and medium access control layers.
Scalable Edge NPU IP for Generative AI
Ceva-NeuPro-M is a scalable NPU architecture, ideal for transformers, Vision Transformers (ViT), and generative AI applications, …
1G to 50G Single-Port MACsec Engine with TSN support
The MACsec-IP-161 is a versatile MACsec solution for silicon devices that require plug-and-play MACsec processing for an Ethernet…
The MIMO Decoder accepts two independent input streams, and the channel estimation matrix.
CCSDS AR4JA LDPC Decoder & Encoder
The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding diff…
Xilinx Ultra Scale NVME Host IP
The LDS NVME HOST K7U IP is one of the most flexible NVME HOST IP in the market.