USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
The Combo PHY is a USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process.
- TSMC
- 28nm
- HPC+
- In Production
USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
The Combo PHY is a USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process.
Advanced graphics and compute acceleration on power constrained devices
Designed for efficiency.
Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-effic…
USB3.0/PCIe2.0 Combo PHY in TSMC28HPC+
USB3PCIE20T28HPCP is a USB3.0 and PCIe 2.0 Combo PHY IP solutoin designed for a mobile and data consumer applications in T28nm pr…
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP
The PCIe2.0 PHY IP is a physical layer (PHY) IP solution designed for mobile and consumer applications.
The silicon-proven Gigabit Ethernet IP core provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Medi…
Fast Ethernet Media Access Controller
The Fast Ethernet Media Access Controller (FEMAC) with AHB or AXI Interface core incorporates the essential protocol requirements…
The 10/100 Ethernet Media Access Controller (MAC) IP core is compliant with the Ethernet IEEE 802.3-2002 standard and has passed …
Gigabit Ethernet with IEEE 1588 and AVB
The Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard and supports protocol ext…
The Ethernet Media Access Controller IP is an embedded Fast Ethernet controller module.
NVMe Gen5 Controller - Enhances data transfer speeds and reduces latency for storage systems
The NVMe Gen 5 Controller is engineered to harness the power of PCIe Gen 5, delivering up to 32 GT/s per lane for significantly f…
IP for Automotive Applications
M31 provides the variety IP types which meet ISO 26262 vehicle function safety requirements for the different applications in the…
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well…
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCI Express® (PCIe®) is architected…
10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
Low-power, long-reach, multi-protocol PHY for PCIe 4.0 The Cadence® 10Gbps multi-protocol PHY IP provides a flexible PHY IP that …
10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
SerDes requirements for system-on-chip (SoC) designs are becoming increasingly demanding and must support increasing numbers of p…
The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect va…
7 Series Integrated Block for PCI Express (PCIe)
Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
7 Series Gen2 Integrated Block for PCI Express (PCIe)
Xilinx provides a 7 Series FPGA solution for PCI Express® (PCIe) to configure the 7 Series FPGA Integrated Block for PCIe and inc…
Virtex-6 Integrated Block for PCI Express (PCIe)
Xilinx provides a Virtex-6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex-6 FPGA Integrated Block for PC…