USB 1.1.OTG PHY IP, OTG, UMC 90nm SP process
USB 1.1 OTG PHY, UMC 90nm SP/RVT Low-K Logic process.
- UCIe 1.1
- UMC
- 90nm
- SP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
USB 1.1.OTG PHY IP, OTG, UMC 90nm SP process
USB 1.1 OTG PHY, UMC 90nm SP/RVT Low-K Logic process.
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 90nm SP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0mA, Pulse Width Modulator, UMC 90nm SP/RVT Low-…
RC Oscillator IP, Output: 10MHz, UMC 90nm LL process
Internal-RC, trimmable fixed frequency 10MHz.
D/A Converter IP, 18 bits, Audio Codec, UMC 90nm SP process
18-Bit MONO Sigma-Delta Digital-to-Analog converter Codec with speaker driver, UMC 90nm SP/RVT Low-K Logic process.
Voltage Detector IP, 4 Levels, UMC 65nm LL process
4-Level Voltage Detector for USB-OTG, UMC 65nm LL Logic/RVT Low-K process and 2.5V overdrive 3.3V device.
USB 1.1.OTG PHY IP, OTG, UMC 65nm SP process
USB 1.1 On-The-Go PHY, UMC 65nm SP/HVT Logic Low-K process.
DC-DC IP, Input: 3.3V, Output: 5V/100mA, UMC 65nm SP process
Boosting voltage from 3.3V to 5V, 100mA driving capability, Ivcca=200uA @ Idrive=0, Pulse Width Modulator, UMC 65nm SP/HVT Logic …
Input 25M-500MHz, output 1000M-1500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process.
RC Oscillator IP, Output: 12KHz, UMC 65nm LL process
Internal-RC, trimmable fixed frequency 12KHz.
RC Oscillator IP, Output: 50MHz, UMC 65nm SP process
Internal-RC, trimmable fixed frequency 50MHz, Input 0.9V-1.1V, VBG=0.5V, UMC 65nm SP/RVT Logic Low-K process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 65nm SP process
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT Logic process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 500MHz - 1GHz, UMC 65nm SP process
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 65nm SP/RVT Logic process.
Single Port SRAM Compiler IP, 5.6um2 bit cells, Synchronous, UMC 0.18um eFlash/G2 process
UMC 0.18um e-flash GII Logic process synchronous Single Port SRAM memory compiler.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type (with Self-Test Circuit), Power On Reset, UMC 0.18um GII Logic process.
Power on Reset IP, Input: 1.8V, UMC 0.18um G2 process
Vrr=1.2V Vfr=1.0V, input 1.8V, Core type, Power On Reset, UMC 0.18um GII Logic process.
RC Oscillator IP, Output: 80MHz, UMC 0.18um G2 process
Internal-RC, trimmable frequency 80MHz.
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.75V Vfr=0.65V, input 1.2V, Core type, Power On Reset, UMC 0.13um HS/FSG Logic process.
Power on Reset IP, Input: 1.2V, UMC 0.13um SP/FSG process
Vrr=0.76V Vfr=0.66V, input 1.2V, Core type, Power On Reset, UMC 0.13um SP Logic(FSG) process.
RC Oscillator IP, Output: 70MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz.
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process.