Vendor: NTLab Category: PLL

Wide band 3Ghz-6GHz fractional phase-locked loop

It is a phase-locked loop frequency synthesizer (PLL) with integer-N/fractional-N modes based on fully integrated wide band LC-VC…

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TSMC 65nm GP Silicon Proven View all specifications

Overview

It is a phase-locked loop frequency synthesizer (PLL) with integer-N/fractional-N modes based on fully integrated wide band LC-VCO with range from 3 GHz to 6 GHz with good phase noise performance. It work with reference frequency from 5 MHz to 50 MHz or external signal source
with frequency up to 500 MHz. Phase-frequency divider compare frequency can be equal or 2,3,4...63 times lower than reference. VCO frequency N-divider has rogrammable coefficient of division with step 1 in range 4 to 2047 modulated with 4-order 24bit DSM. Phase-frequency detector has built-in lock detector circuit. Charge pump scheme with ADC and adjustable output current allow compensation VCO gain variation within band and keep loop parameters constant. Integrated low-pass loop filter has adjustable values of resistance and capacitance for tune loop and get best phase-noise performance.
The PLL is designed using TSMC 65 nm CRN65LP technology.

Key features

  • TSMC CMOS 65 nm
  • Fractional-N/Integer-N phase-locked loop modes
  • Wide frequency range from 3 GHz to 6 GHz
  • Good phase noise perfomance
  • Fully integrated VCO
  • Fully integrated loop filter with ability to use external loop filter
  • Built-in lock detection circuit
  • High reference frequency spurious rejection
  • Adjustable value of charge pump output current
  • Built-in ADC for measuring VCO control voltage value
  • Digital loop gain compensation
  • Low current consumption
  • Adjustable power supply voltage

Block Diagram

065TSMC_PLL_09 block diagram

Applications

  • RF receivers, transmitters, transceivers
  • High frequency clock generation

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 65nm GP Silicon Proven

Specifications

Identity

Part Number
065TSMC_PLL_09
Vendor
NTLab
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab
HQ: Lithuania
Contact NTLab

Learn more about PLL IP core

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How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Wide band 3Ghz-6GHz fractional phase-locked loop?

Wide band 3Ghz-6GHz fractional phase-locked loop is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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