Learn more about PLL IP core
Fractional-N PLLs are a useful class of PLLs and not well understood. This paper explains in simple terms how these differ from a regular integer PLL. Common applications are listed along with a brief description of the key performance parameter – jitter.
Like most types of circuits, there is no such thing as a "one size fits all" PLL. This article will explore the trade-offs in PLL performance and design and look for a solution to most SOC PLL needs.
The economics of a system-on-chip ASIC have evolved over the last decade, driven by forces such as cost to yield a transistor, wafer defect density and chip yield, and the drive for greater performance and efficiency. As process nodes continued to shrink from 28nm down to 3nm, we observed Moore’s Law begin to break down, and the cost to yield 100 million transistors normalized to 28nm was either flat or, arguably, increased.
At Silicon Creations, we have developed a power and area optimized, flexible and programmable PMA (Physical Medium Attachment) architecture that can be reliably ported to different process nodes and scaled across protocol generations as data rates increase. It is called the Multi-Protocol PMA, or MP-PMA for short.
In this article we provide an introduction to DP, talk about the various factors that IC designers will want to consider when integrating the DP functionality into their SOC, and present at a high-level the solutions Silicon Creations provides in this area.
This presentation is about a problem we at Silicon Creations have seen quite often when our, or others’ PLLs are used in complex SoCs. Although the design team usually implements the PLL correctly in the chip with the right supplies connected the right ways, we have often seen that designers overlook the significant impact that their floorplan and power supply plan have on the clock as it travels from the PLL to the circuits the PLL is clocking.
