Video Timing Generator

The VID_TIMING_GEN IP Core is a fully configurable video timing generator with the ability to support any video resolution up to 216 x 216 pixels in size. The module is compatible with a wide range of video DACs, encoders and transmitters and provides a flexible solution for displaying digital or analogue video on an external TV, monitor or flat panel display. The module is capable of clock speeds in excess of 400 MHz on some FPGA platforms, making it ideal for the latest generation HD and UHD video solutions.

Input pixels and syncs are read on the rising edge of clk_a (the system clock) when pixin_val and pixin_rdy are both active high. The input signal pixin_vsync is coincident with the first active pixel in a frame and the signal pixin_hsync is coincident with the first active pixel in a line. (Note that these sync signals should not be confused with true video timing signals. Their purpose is to delineate the first pixel in a frame and the first pixel in a line only).

After resynchronizing the input pixels to the pixel-clock domain (clk_b), the controller locks to the first frame (or field) of video. Once frame-lock is achieved, pixels are supplied on demand to the video timing control unit. This module generates the correct RGB video, sync and blanking information depending on the chosen timing parameters.

• Synthesizable, technology independent IP Core for FPGA, ASIC and SoC
• Supplied as human readable VHDL (or Verilog) source code
• Simple FIFO input interface
• Programmable RGB channel data width (8,10,12,14-bits etc.)
• Highly versatile architecture supports direct connection to a wide range of video DACs, video encoders and DVI/HDMI transmitters
• VSYNC, HSYNC, CSYNC, DE and BLANKING outputs
• Fully programmable timing parameters
• Supports industry standard (VESA, CEA-861, ITU-R BT.656 etc.) and fully custom video modes (both progressive and interlaced formats)
• Future-proof design supports resolutions up to 216 x 216 pixels (8K video and above)
• Independent system and pixel clocks supporting frequencies of 400 MHz+ on basic FPGA platforms1
• Compatible with all Zipcores video IP Cores

• HD, UHD and SUHD next generation digital video
• Legacy (SD) and analogue video applications
• Computer monitors and flat-panel displays
• Digital TV and multimedia solutions