Video Test Pattern Generator

The VIDEO TEST PATTERN GENERATOR IP Core is a versatile test pattern generator capable of producing a range of video test patterns in colour, greyscale and monochrome formats. The module is invaluable during the prototyping of digital video systems. It’s also ideal for any video project that requires a reference video source.

Pixels and syncs are generated on a rising clock-edge when pixout_val is high and pixout_rdy is high. The signal pixout_vsync is active high when the first pixel of a frame is output. The signal pixout_hsync is active high when the first pixel of a line is output. The pixout_field flag indicates either an odd or even field when interlaced mode is enabled.

By enabling or disabling the pixout_rdy signal, the flow of pixels out of the test pattern generator may be easily controlled by the downstream module. The test pattern generator has 'infinite' video bandwidth. In other words, the generation of output pixels is only limited by the system pixel clock frequency.

The video output resolution is controlled by the parameters tpg_ppl and tpg_lpf. The colour, type and dimensions of the test pattern are determined by the parameters tpg_intl, tpg_mode, tpg_type, tpg_width and tpg_log2w.

• Synthesizable, technology independent IP Core for FPGA, ASIC and SoC
• Supplied as human-readable VHDL (or Verilog) source code
• Test patterns generated as 24-bit RGB-video
• Supports all video resolutions up to 216 x 216 pixels
• Progressive and interlaced formats
• Colour, greyscale or monochrome outputs
• Bars, squares, lines and 'bouncing ball' display
• Programmable pattern width and line spacing
• Simple valid-ready output flow control
• Fully configurable output video resolution
• Output pixels generated at 1 pixel/clock
• Compatible with all Zipcores video IP cores

• Digital video testing and prototyping
• Standard reference video outputs
• Simple screen savers