High Speed Ethernet 100G MAC IP
The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 s…
- Ethernet
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
High Speed Ethernet 100G MAC IP
The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 s…
112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
The 112G Ethernet PHY IP, an integral part of the 400GbE/800GbE Ethernet solution enables long reach (LR), medium reach (MR), ver…
1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
The HDCP 2.3 Embedded Security Modules (ESMs) on DisplayPort are autonomous modules that provide designers with a and robust tran…
USB-C 3.1/DisplayPort 1.4 IP Subsystem Solution
Synopsys has pre-integrated USB-C 3.1/DisplayPort 1.4 IP into a single subsystem solution to save customers more than two enginee…
SuperSpeed USB 3.1 Host Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
SuperSpeed USB 3.1 DRD Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
SuperSpeed USB 3.1 Device Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
DisplayPort 1.4 TX PHY, TSMC N5, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for…
Die-to-Die, AIB 2.0 PHY Ported to Intel 16, North/South (vertical) poly orientation
The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
D2D Controller addon for D2D SR112G PHY with CXS interface
The Die-to-Die Controller IP, optimized for latency, bandwidth, power, and area, enables efficient inter-die connectivity in serv…
UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A PHY for Advanced Package (x64) in TSMC N5, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x16) in SS SF4X, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A (Gen2) PHY for Advanced Package (x64) in SS SF4X, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x16) in SS SF2, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A PHY for Advanced Package (x64) in SS SF2, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …