Vendor: Synopsys, Inc. Category: Multi-Protocol PHY

25G PHY, GF 12LP x2 North/South (vertical) poly orientation

The multi-lane Multi-Protocol 25G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking a…

GlobalFoundries 12nm LP View all specifications

Overview

The multi-lane Multi-Protocol 25G PHY IP is part of a high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is small in area and provides a low active and standby power solution that supports multiple electrical standards, including PCI Express (PCIe) 4.0, 25G and 100G Ethernet, Cache Coherent Interconnect for Accelerators (CCIX), SATA and other industry-standard interconnect protocols. Using leading-edge design, analysis, simulation, and measurement techniques, the multi-protocol 25G PHY delivers signal integrity and jitter performance that exceeds the standards electrical specifications.

The configurable transmitter and receiver equalizers along with Continuous Calibration and Adaptation (CCA) enable designers to control and optimize signal integrity and performance across voltage and temperature variations. The PHY provides advanced power management features for both standby and active power. The embedded bit error rate tester (BERT) and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Coding Sublayers (PCS) and digital controllers/Media Access Controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.

Key features

  • Supports 1.25 to 25.8 Gbps data-rate
  • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
  • Supports x1 to x16 macro configurations with aggregation and bifurcation
  • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
  • Ethernet Electrical Energy Efficient (EEE)
  • Reference clock sharing for aggregated macro configurations
  • Continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)
  • Embedded bit error rate tester (BERT) and internal eye monitor
  • Supports IEEE 1149.6 AC Boundary Scan

Block Diagram

dwc_25g_phy_gf12lp_x2ns block diagram

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP —

Specifications

Identity

Part Number
dwc_25g_phy_gf12lp_x2ns
Vendor
Synopsys, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Synopsys, Inc.
HQ: USA

Learn more about Multi-Protocol PHY IP core

Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP

In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 25G PHY, GF 12LP x2 North/South (vertical) poly orientation?

25G PHY, GF 12LP x2 North/South (vertical) poly orientation is a Multi-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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