Synopsys, Inc.
•
HQ:
USA
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
- Controller + PHY + 1
Compare 1,936 Synopsys, Inc. IP Cores from 1 vendors
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Synopsys, Inc.• HQ: USA
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
- Controller + PHY + 1
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Synopsys, Inc.• HQ: USA
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
- Controller + PHY + 1
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HBM3 Solution enabling access to HBM3 Controller in TSMC N5 1.2V
Synopsys, Inc.• HQ: USAThe HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard.
- Controller
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HBM3 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N5 1.2V
Synopsys, Inc.• HQ: USAThe HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard.
- Controller + PHY
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Synopsys, Inc.• HQ: USA
The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3, DDR3L (1.3…
- Controller + PHY + 1
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Synopsys, Inc.• HQ: USA
The Gen 2 DDR multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard LPDDR2, LPDDR3…
- Controller + PHY + 1
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Synopsys, Inc.• HQ: USA
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
- Controller + PHY + 1
- DDR4
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Synopsys, Inc.• HQ: USA
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…
- Controller + PHY + 1
- DDR4
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Synopsys, Inc.• HQ: USA
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…
- Controller + PHY + 1
- DDR4
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Synopsys, Inc.• HQ: USA
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…
- Controller + PHY + 1
- DDR4
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Synopsys, Inc.• HQ: USA
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…
- Controller + PHY + 1
- DDR4
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Synopsys, Inc.• HQ: USA
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- Controller
- DDR2 + 2
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Synopsys, Inc.• HQ: USA
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- Controller
- DDR2 + 2
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DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
Synopsys, Inc.• HQ: USAThe Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- Controller
- DDR2 + 2
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Synopsys, Inc.• HQ: USA
The LPDDR5/4/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-packag…
- Controller + PHY + 1
- LPDDR5
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LPDDR5/4/4X PHY - SS 14LPU for Automotive AEC-Q100 Grade 1
Synopsys, Inc.• HQ: USAThe LPDDR5/4/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-packag…
- Controller + PHY + 1
- LPDDR5
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LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X
Synopsys, Inc.• HQ: USAThe LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC st…
- Controller
- LPDDR4 + 1
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LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
Synopsys, Inc.• HQ: USAThe LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC st…
- Controller
- LPDDR4 + 1
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Synopsys, Inc.• HQ: USA
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
- Controller + PHY + 1
- LPDDR5 + 1