Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
- UMC
- 55nm
- LP
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed in Taipei Stock Exchange, ticker 3035.
Standard Cell PowerSlash(TM) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 12-Track Generic Core Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Low-K Logic process UHS Cell Library.
Standard Cell (Ultra High Speed) Library IP, HVT, 12 tracks, UMC 55nm eHV process
UMC 55nm HV/HVT Low-K Logic process high speed Standard Core Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/RVT Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm SP process
UMC 55nm SP/HVT Logic process 7-Track Mini Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 7-Track Mini-Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Low-K Logic process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Cell Library with LPLUS (C38 RVT).
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 RVT).
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library wtih LPLUS (C38).
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 LVT).
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library.