Faraday Technology IP Cores

DDR3/DDR3L/LPDDR2 combo PHY ( not support DDR3 leveling function), command / address block,UMC 40nm LP/RVT LowK Logic Process.

• Controller + PHY + 1
• UMC
• 40nm
• LP

DDR3 Combo PHY Data Block for solder bump application; UMC 40nm LP/RVT Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 40nm
• LP

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP

UMC 55NM SP-RVT with 2.5V device process 16BIT DDR23 COMBO DATA PHY for two layer PCB board usage

• Controller + PHY + 1
• DDR2
• UMC
• 55nm
• SP

DDR3 Combo PHY Compensation Block for solder bump application; UMC 40nm LP/RVT Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 40nm
• LP

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 28nm
• HPC

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 40nm
• LP

DDR3 Combo PHY COMM/ADDR Block for 2-rank and solder bump application; UMC 40nm LP/RVT Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 40nm
• LP

Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Log…

• Controller + PHY + 1
• UMC
• 55nm
• SP

UMC 55NM SP-RVT with 2.5V device DDR23 COMBO PHY CMD/ADDR Block for 2 layer PCB board usage

• Controller + PHY + 1
• DDR2
• UMC
• 55nm
• SP

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 110nm
• HS
• Pre-Silicon

DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process

• Controller
• UMC
• 110nm
• HS
• Pre-Silicon

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 110nm
• HS
• Pre-Silicon

DDR1/MDDR PHY Data block ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP
• Pre-Silicon

DDR1/MDDR PHY CMD/ADDR BLOCK ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP
• Pre-Silicon

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

• Controller + PHY + 1
• UMC
• 40nm
• LP

Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

• Controller + PHY + 1
• UMC
• 40nm
• LP

High performance 8-bit micro-controller with 256 bytes on-chip Data RAM, three 16-bit timer/counter, and two 16-bit dptr; UMC 0.1…

• UMC
• 180nm
• BCD
• In Production

FTMCP100 is a video and image compression / decompresion IP core that supports the MPEG-4 (ISO/IEC 14496-2) and JPEG (ISO/IEC 109…

• MPEG-4
• UMC
• 130nm
• HS
• Pre-Silicon

This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synt…

• UMC
• 40nm
• LP