MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process
MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process
- MIPI D-PHY
- UMC
- 28nm
- HPC
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed in Taipei Stock Exchange, ticker 3035.
MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process
MIPI Receiver, DPHY V1.2 RX ; UMC 28nm HPC process
MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process
MIPI Receiver, DPHY V1.1 RX ; UMC 28nm HPC process
MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC+ Process
MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC+ Process
MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process
MIPI DPHY Reciever 80Mbps~2.5Gbps ; UMC 28nm HPC Logic Process
1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process
1.8V Sub-LVDS Receiver 650Mbps; UMC 28nm HPC process
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process
100MHz single-ended to differential clock buffer for UMC 40nm LP.
100MHz single-ended to differential clock buffer for UMC 40nm LP.
LVDS Transmitter 700Mbps; UMC 28nm HPC Process
LVDS Transmitter 700Mbps; UMC 28nm HPC Process
2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout )
2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process.
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces
3.3V FPD-link LVDS Transmitter 16~100MHz; UMC 28nm HPC plus proces
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVDSRX080HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0L, UMC 55nm LP/RVT LowK Logic Process
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process
The bias block only for FXLVRX080HF0F, UMC 55nm eflash/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
The bias block only for FXLVRX050HH0L, UMC 40nm LP/RVT LowK Logic Process
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip
LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process
LVDS RX IO PAD 300 Mbps with combo GPIO , UMC 55nm eflash/RVT LowK Logic Process
3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process
3.3v LVDS RX IO 1.25Gbps, UMC 40nm LP/RVT LowK Logic Process
8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process
8 Lanes LVDS RX IO PAD, UMC 40nm LP/RVT LowK Logic Process
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process