Faraday Technology IP Cores

2.5V FPD-link LVDS Transmitter 16~178.6MHz; UMC 40nm LP Low-K process

• UMC
• 40nm
• LP

3.3v LVDS RX, 3 data lane and 1 clock lane using UMC 40nm LP/RVT LowK Logic Process

• UMC
• 40nm
• LP

UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format

• UMC
• 28nm
• HPC

10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process

• UMC
• 40nm
• LP
• Silicon Proven

10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process

• UMC
• 28nm
• HPC

compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .

• Controller
• DDR3
• UMC
• 40nm
• LP
• Pre-Silicon

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Proce…

• Controller + PHY + 1
• UMC
• 40nm
• LP
• Pre-Silicon

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP
• Pre-Silicon

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP
• Pre-Silicon

Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 55nm
• LP
• Pre-Silicon

Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 55nm
• SP
• Pre-Silicon

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device (16Bit)

• Controller + PHY + 1
• DDR2
• UMC
• 40nm
• LP
• Pre-Silicon

DDR3/2 COMBO PHY DATA BLOCK for 2 layer 8 bits DDR3 PCB ; UMC 40LP/RVT LowK Logic Process with 2.5V device

• Controller + PHY + 1
• DDR3
• UMC
• 40nm
• LP
• Pre-Silicon

DDR23 COMBO PHY Data Block ; UMC 40nm LP/RVT LowK Logic Process with 2.5V device

• Controller + PHY + 1
• DDR2
• UMC
• 40nm
• LP
• Pre-Silicon

DDR2/3 PHY Combo PHY data block (1.0v SP & 2.5V device); UMC 90nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR2
• UMC
• 90nm
• SP
• Silicon Proven

Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• UMC
• 55nm
• SP
• Pre-Silicon

Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 55nm
• LP
• Pre-Silicon

Compensation Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

• Controller + PHY + 1
• DDR3
• UMC
• 55nm
• SP
• Pre-Silicon

DDR23 COMBO PHY compensation Block ; UMC 40LP/RVT LowK Logic Process with 2.5V device

• Controller + PHY + 1
• DDR2
• UMC
• 40nm
• LP
• Pre-Silicon

DDR2/3 COMBO Compensation block (2.5V IO device) ; UMC 90nm SP-RVT LowK Logic Porcess

• Controller
• DDR2
• UMC
• 90nm
• SP
• Silicon Proven