Vendor: SmartDV Technologies Category: USB

USB PD IIP

USB PD interface provides full support for the USB PD synchronous serial interface, compatible with USB 3.1/3.0/2.0 and 1.0 speci…

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Overview

USB PD interface provides full support for the USB PD synchronous serial interface, compatible with USB 3.1/3.0/2.0 and 1.0 specifications. Through its USB PD compatibility, it provides a simple interface to a wide range of low-cost devices. USB PD IIP is proven in FPGA environment. The host interface of the USB PD can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

USB PD IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with USB Power Delivery Specification 3.1/3.0/2.0 and 1.0
  • Supports Cable plug communication
  • Supports all Resets: Hard, Soft and Cable Resets
  • Supports all types of packets.
  • Supports BFSK and BMC signaling of physical layer
  • Support BIST.
  • Supports Timers as per specification
  • Supports Counters as per specification
  • Supports data role swap and power role swap
  • Supports Structured and Unstructured VDM
  • Supports Device and System Policy
  • Supports injecting timing variations in physical layer.
  • Supports all Swappings: Power role, Data role, Fast power role and Vconn swap
  • Supports chunked transaction
  • Supports included extended power supply capabilities and status.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.

Block Diagram

USB_PD IIP block diagram

Benefits

  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The USB PD interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
USB_PD IIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about USB IP core

What Designers Need to Know About USB Low-Power States

In addition to performance and interoperability, achieving low power has been one of the requirements for industry standards specifications. Some of the key specifications like Universal Serial Bus (USB), PCI Express (PCIe), and MIPI have defined power saving features for burst traffic. This whitepaper explains how Synopsys USB IP offers low power using various low power states that go beyond the basic features.

Frequently asked questions about USB IP cores

What is USB PD IIP?

USB PD IIP is a USB IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this USB?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this USB IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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