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Vendor:
Faraday Technology
Category:
SRAM
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.
Overview
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 55nm | 55nm 550 nm | Pre-Silicon |
Specifications
Identity
Part Number
FSF0F_L_SHRED
Vendor
Faraday Technology
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan
Learn more about SRAM IP core
The Platform Based SOC Design that Utilizes Structured ASIC Technology
The Platform Based SOC Design that Utilizes Structured ASIC Technology
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Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
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Frequently asked questions about SRAM IP cores
What is UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.?
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy. is a SRAM IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc Pre-Silicon.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.