TSMC N5A 1.2V/1.8V OSC AG2 Platform

Jian Yang, Sween Kang (Synopsys)

This paper presents some key concepts necessary to design and build high-quality, mixed-signal IP in 28-nm or smaller geometries. The paper addresses specific design, layout, and verification techniques to address challenges posed in 28-nm technology nodes. Specifically, the paper focuses on three main areas where 28-nm technologies pose some unique challenges, Low-Power Design, Restricted Design Rules, and Design for Yield. Several design examples are presented, highlighting key techniques employed in the Synopsys® DesignWare® Mixed-Signal Intellectual Property portfolio.

In this paper, we present a flexible ring oscillator IP designed for a 40nm CMOS technology, whose oscillation frequency can be chosen from 200kHz to 20MHz. It was developed using a new design approach, in which analog IPs are designed from scratch to be flexible, employing modular blocks that can be easily customized. The IP is silicon proven. It works with a supply voltage of 1.2V and features 5% frequency accuracy, occupying an area of 0.0022mm2.

This article reviews the functional-safety attributes of Classical CAN and CAN FD, then explains how CAN XL preserves and extends them. It also discusses higher-layer safety protocols, fault-tolerant CAN XL controller implementations, and CANsec, the CAN XL security extension inspired by the MACsec model. Finally, it highlights how the CAST CAN XL controller IP and CANsec acceleration IP can support the efficient deployment of safety- and security-capable in-vehicle networks.

This article outlines Key ASIC R&D team's upcoming PLL suitable for high-speed SerDes having ultra low jitter with LC- tank VCO, and supporting up to 16 GHz output clock to sample the data.

This article outlines our R&D team's upcoming PLL suitable for high-speed SerDes having ultra low jitter with LC- tank VCO, and supporting up to 16 GHz output clock to sample the data.