Vendor: Global UniChip Corp. (GUC) Category: FIFO / CAM

TSMC CLN6FF Ternary Content Addressable Memory Compiler with Column Redundancy

IGMTLSX07A is a synchronous LVT / ULVT periphery high-density ternary content addressable memory (TCAM) with column redundancy fe…

TSMC 6nm N6FF Pre-Silicon View all specifications

Overview

IGMTLSX07A is a synchronous LVT / ULVT periphery high-density ternary content addressable memory (TCAM) with column redundancy feature. It is developed with TSMC 6nm 0.75V/1.8V CMOS LOGIC FinFET Process. Different combinations of words and bits could be used to generate the most desirable configurations.
Given the desired size and timing constraints, the IGMTLSX07A compiler is capable of providing suitable synchronous TCAM instances models within minutes. It is capable of automatically generating the data sheets, Verilog behavioral simulation models, Place & Route (P & R) models, and test patterns for use in ASIC designs. The duty cycle length could be neglected as long as setup/hold time and minimum high/low pulse widths requirements are satisfied. This allows a more flexible clock falling edge during each operation.

Key features

  • Ternary Content Addressable Memory (TCAM) operates within voltage range from 0.675V to 0.825V and junction temperature range from -40°C to 125°C. The available supported macro size is configurable from 32bits to 80K bits.
  • Pins and metal layers
  • 1P4M (1X_h_1Xa_v_1Ya_h): 4 metal layers used and top metal is MYa
  • Power mesh supported with M4 pins
  • General feature
  • TSMC 16T 0.126um2 NOR TCAM bit cell
  • Full-customized design to optimize for performance, power and area
  • Two arrays, Data and Mask arrays, used to encode 0, 1 or X
  • Memory control pins for read/write and compare
  • Global mask input for bit-write and masked-key search capability
  • Dynamic compare power saving by appropriately configuring bank enable pins
  • Valid bit per entry
  • MATCHLINE outputs
  • Column redundancy
  • Word and Bit segment types for area and performance adjustment
  • Dual rail design to support Dynamic Voltage Frequency Scaling (DVFS) application
  • Support BIST/ECC code
  • Frequently used EDA model support
  • BIST compiler feature
  • BIST RTL compiler enabling TCAM complete read, write, search function tests with various data background
  • At-speed test for column repair TCAM compiler
  • JTAG interface to program basic and advanced types of algorithm
  • Hierarchical verification flow: TCAM local, block level and SOC level verification
  • Support the JTAG stream for various BIST algorithm tests and programmable tests
  • With eFuse inserted, generate the JTAG stream for BIST tests, eFuse programming and BISR test
  • ECC system feature
  • Pure soft macro RTL compiler to support SEC/DED for Read/Write operation and SCRUB mode
  • Support auto scrub mode with programmable timing interval
  • External scrub can be requested by system with interrupt control
  • External standard SRAM can be used for ECC bits
  • Support RTL wrapper for system integration and test bench for verification

Silicon Options

Foundry Node Process Maturity
TSMC 6nm N6FF Pre-Silicon

Specifications

Identity

Part Number
IGMTLSX07A
Vendor
Global UniChip Corp. (GUC)
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Frequently asked questions about FIFO / CAM IP cores

What is TSMC CLN6FF Ternary Content Addressable Memory Compiler with Column Redundancy?

TSMC CLN6FF Ternary Content Addressable Memory Compiler with Column Redundancy is a FIFO / CAM IP core from Global UniChip Corp. (GUC) listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this FIFO / CAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this FIFO / CAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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