Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: SRAM

TSMC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler

VeriSilicon TSMC 0.15um Low Voltage Process High-Speed Synchronous Memory Compiler optimized for Taiwan Semiconductor Manufacturi…

TSMC 150nm LV Pre-Silicon View all specifications

Overview

VeriSilicon TSMC 0.15um Low Voltage Process High-Speed Synchronous Memory Compiler optimized for Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.15?m Logic Low Voltage 1P7M Salicide 1.2/3.3V process can flexibly generate memory blocks by a friendly GUI or shell commands.
The compiler supports a comprehensive range of word and bits. While satisfying speed and power requirements, it has been optimized for area efficiency.
VeriSilicon TSMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, 6 or 7 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.

Key features

  • High Density
  • High Speed
  • Size Sensitive Self-Time Delay for Fast Access
  • Automatic Power Down
  • Tri-State Output(SRAM only)
  • Write Mask Function(SRAM & Register File)

Silicon Options

Foundry Node Process Maturity
TSMC 150nm LV Pre-Silicon

Specifications

Identity

Part Number
TSMC15LV MC
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is TSMC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler?

TSMC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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