True Random Number Generator (TRNG) IP

High-Quality Entropy for Secure Key Generation and Cryptographic Operations

The TRNG IP delivers NIST- and BSI-compliant entropy for secure embedded and SoC designs. With robust health testing and digital or analog implementation options, our TRNGs provide the foundation for trusted key generation, encryption, and authentication in mission-critical applications.

NIST & BSI Compliant Entropy Sources

Entropy is verified against SP800-90B (entropy quality), AIS31 (randomness assurance), and SP800-22 (statistical distribution). The TRNG supports DRBGs compliant with SP800-90A.

Digital & Analog Implementations

Choose a fully digital noise source for ease of integration, or analog implementations for higher-quality entropy in lower-power applications.

In-Built Health Testing

Includes continuous entropy health tests and conditioning logic to identify faults, degradation, or bias in real-time.

Security-Ready Architecture

Perfect for secure boot, cryptographic key generation, and trusted identity provisioning — whether stand-alone or integrated in a secure element.

• Standards-Compliant Entropy: Validated against NIST SP800-90B, AIS31, and SP800-22 statistical test suites
• Digital & Analog Options: Choose the right entropy source for your performance, integration, or cost targets
• In-Built Health Checks: Conditioning and health test logic ensures ongoing randomness integrity
• Secure Key Generation: Ideal for feeding cryptographic cores, secure boot, and identity provisioning
• High Throughput: Digital TRNG supports sampling rates up to 100 Mbit/s, ideal for scalable systems
• Seamless SoC Integration: Supplied with RTL, constraints, and documentation to simplify implementation

• 100 Mbit/s Throughput: Verified sampling rates ensure entropy scaling for high-demand crypto applications
• SP800-90A/B Compliant: Tested against NIST standards for entropy, randomness, and statistical reliability
• Health & Conditioning Logic: Includes on-chip detection of entropy degradation and bias correction mechanisms
• RTL & Integration Assets: Delivered with RTL netlist, Verilog models, constraints, and documentation