DRBG IP Core

DRBG IP Cores perform deterministic random bit generation in compliance with the standards and guidelines defined in 'NIST SP 800-90A'. This standard specifies methods for generating deterministic random bits suitable for cryptographic applications.

DRBG IP Core includes the CTR-DRBG mechanism, which uses an AES-128. VHDL is used as the Hardware Description Language of the IP Core. DRBG IP Cores support various operations, including instantiation with and without personalization strings, reseeding with and without additional input, and generating random bits with or without prediction resistance and with and without additional input. 

• Compliant with NIST SP 800-90A.
• supports the operations listed below:
  • instantiate with and without Personalization String         
  • reseed with and without Additional Input          
  • generate with and without Prediction Resistant and with and without Additional Input      
• has fully stallable input and output interface.

• Encrypted Netlist
• Synthesis Scripts
• Comprehensive Documentation
• DRBG Validation System Testbenches in SystemVerilog