Vendor: NTLab Category: DAC

12-bit 1-channel up to 1 MSPS R/2R DAC

028TSMC_DAC_01 is a 12-bit digital to analog converter (DAC) with sample rates up to 1 MSPS.

12 Bit TSMC 28nm Pre-Silicon View all specifications

Overview

028TSMC_DAC_01 is a 12-bit digital to analog converter (DAC) with sample rates up to 1 MSPS. The block contains four main blocks: reference voltage source, bias voltage source, DAC core and control digital module. DAC core consist of the R/2R matrix and output operational class AB amplifier. The DAC operates directly from VDDIO/VDD33 supplies which are filtered analog supply pins of the chip. Analog voltage references can be generated from internal buffer or supplied externally.

Key features

  • TSMC 28nm eFlash
  • 12-bit resolution
  • Single-ended one channel output
  • External clock
  • Output sampling rate up to 1MSPS
  • Current consumption in operation mode: 0.7mA@ VDDIO=5.0V
  • External input frequency 1MHz
  • Analog IO supply voltage 5.0V (3.3V option)
  • 3.3V supply voltage
  • Core supply voltage 0.9V
  • Automotive compliant: -40?C to +150?C
  • GDS Area ~0.11mm2

Block Diagram

Applications

  • Digital to analog signal conversion
  • Automotive applications
  • Receivers, transceivers
  • Measurement environment

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm Pre-Silicon

Specifications

Identity

Part Number
028TSMC_DAC_01
Vendor
NTLab
Type
Silicon IP

Analog

Resolution bits
12 Bit

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Lithuania

Learn more about DAC IP core

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Frequently asked questions about DAC IP cores

What is 12-bit 1-channel up to 1 MSPS R/2R DAC?

12-bit 1-channel up to 1 MSPS R/2R DAC is a DAC IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this DAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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