PCIe error logging and handling on a typical SoC
This paper details first PCIe errors, error logging and then the error handling on a typical SoC.
Vendor:
Truechip Solutions
Category:
Protocol Bridge
TileLink Verification IP
The TileLink Verification IP provides an effective & efficient way to verify the components interfacing with TileLink bus of an I…
Overview
The TileLink Verification IP provides an effective & efficient way to verify the components interfacing with TileLink bus of an IP or SoC. It is fully compliant with standard TileLink specification from SiFive, Inc. This VIP is a light weight VIP with an easy plug-and-play interface so that there is no hit on the design cycle time.
Key features
- Compliant to TileLink specification from SiFive inc.
- Support for all type of TiLeLink Agents: TileLink Master, TileLink Slave
- Wide range of strict programmable protocol checks
- Slave memory data check
- Bus assertion for all protocol scenarios
- Fully compliant to TileLink crossbar matrix
- Any type of complex TileLink network which follows the acyclic agent graph (DAG).
- Support all types of conformance level with 5 respective channels.
- TL-UL
- TL-UH
- TL-C
- All parameters Widths like data bus, address, size, sources, sinks are configurable.
- Controllable valid and ready assertion with weighted constraints.
- Different modes when ready are not asserted before starting burst.
- A configurable number of cycles for bounded busy periods.
- User can also provide a particular restriction on address
- Single and burst request and response supported
- All 3 types of request-response ordering possible.
- Response on the same cycle
- Response before the last beat received
- Response after some delay of received all beats
- All types of operations are supported as per respective conformance levels.
- Access
- Hint
- Transfer
- All opcodes and param for request and response messages supported for operations on all five channels.
- Can work as any node in the graph of position on a tree.
- Nothing
- Trunk
- Tip (with no Branches)
- Tip (with Branches)
- Branch
- Permission transitions are also supported
- Cap
- Grow
- Prune
- Report
- TrueEye Supported for debugging in graphical and pictorial menar.
Block Diagram
TileLink block diagram
Benefits
- Available in native SystemVerilog, UVM and Verilog
- Unique development methodology to ensure the highest levels of quality
- Availability of Compliance & Regression Test Suites
- Exhaustive set of assertions and cover points with connectivity example for all the components.
- Consistency of interface, installation, operation and documentation across all our VIPs
- 24X5 customer support
- Unique and customizable licensing models
What’s Included?
- TileLink Master/Slave Agent
- TileLink Bus Monitor, Assertion and Scoreboard
- Test Environment & Test Suite:
- Basic and Directed Protocol Tests
- Random Tests
- Error Scenario Tests
- Assertions & Cover Point Tests
- Integration Guide, User Manual, FAQ, and Release Notes
Specifications
Identity
Part Number
TileLink
Vendor
Truechip Solutions
Type
Verification IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Protocol Bridge IP cores
What is TileLink Verification IP?
TileLink Verification IP is a Protocol Bridge IP core from Truechip Solutions listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.