AHB Lite Verification IP

The AHB Verification IP provides a complete solution for Verification of AMBA 3.0 AHB-Lite protocol v1.0 component of a SOC or ASIC. The AHB-Lite Verification IP is fully compliant with standard AMBA 3 AHB-Lite Specification. AMBA 3.0 AHB-Lite VIP is supported natively in SystemVerilog and UVM.

• Fully compliant with AMBA 3.0 AHB-Lite of the ARM specification.
• Supports AHB Lite Operation.
• Configurable as a full AHB Lite Master, Slave.
• Supports Multi-Master and Multi-Slave System(Optional).
• Supports pipelined operation.
• Parameterized data and address widths.
• Supports all transfer types (IDLE, BUSY, NONSEQ & SEQ) and burst transfers (4, 8, 16 bit incrementing and wrapping).
• Supports controllable wait states.
• Supports early burst termination.
• Supports insertion of delays by slave and master.
• Configuration of lock and unlock transfer.
• Supports big endian and little endian mode.
• Supports various error injection and detection.
• Supports Configurable memory in slave operation.

• Available in Pure System Verilog and with UVM methodology Support.
• Unique development methodology to ensure highest levels of quality.
• Availability of Compliance & Regression Test Suites.
• 24X5 customer support.
• Unique and customizable licensing models.
• Exhaustive set of assertions and coverage points with connectivity example for all the components.
• Consistency ofinterface, installation ,operation and documentation across all our VIPs.
• Supports directed random & fully random tests.
• Supports Environment configuration of VIP based on the DUT.
• Includes scoreboard for end to end data integrity check.
• Monitors & checkers for protocol violations.
• Coverage model for functional coverage.

• VIP User’s guide.
• AHB Lite VIP Encrypted source code.
• Sample Test bench Top.
• Sample Scoreboard& Sanity test.
• Assertions and coverage model.