Logic Design Solutions Announces Gen 5 NVMe Host IP on AGILEX 7 R-Tile
France, Gournay sur Marne, September 8 2025 – The Gen5 NVME-HOST-IP on AGILEX 7 R-Tile of Logic Design Solutions is now available. It enables random access, sequential access, Read/Write access and multi-user access. FAT32/EXFAT file system working in RAID0 is available as an option.
To show these features, several demos, from which customers can re-use to start their project, are ready to use :
- Sequential access on one disk, two disks or four disks with or without FAT32/EXFAT.
- Random access evaluation.
- Simultaneous write access and read access on one disk, two disks or four disks .
- CPU (C Source code provided) or State Machine (VHDL provided) Demo.
All of these features in one single IP at PCIe Gen5 speed.
No need anymore to buy separate IP for each function.
Related Semiconductor IP
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- NVMe IP core -- Directly connect PCIe SSD without external memory
- NVMe Verification IP
- NVMe Host Controller
- NVMe 2.3 Verification IP
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- Logic Design Solutions Introduces the first NVMe Host IP on PolarFire FPGA
- Logic Design Solutions Introduces the first NVMe HOST IP on POLARFIRE SoC FPGA
- Logic Design Solutions Launches NVME Host IP on Xilinx Ultrascale & Ultrascale Plus FPGA
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