Vendor: Cadence Design Systems, Inc. Category: CAN / CAN-FD / CAN-XL

Simulation VIP for CAN

Cadence provides a mature and comprehensive Verification IP (VIP) for the CAN (Controller Area Network) Protocol.

Verification IP View all specifications

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the CAN (Controller Area Network) Protocol. The Cadence® Verification IP for CAN provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CAN helps you reduce time to test, accelerate verification closure and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

CAN is a serial communications protocol with multi-master bus access, time synchronization, and high error-detection capability. Its domain of application ranges from high-speed networks to low-cost multiplex wiring.

Supported specifications: CAN protocol versions 2.0 and 1.0, Flexible Data-Rate version 1.0, CAN XL protocol CiA 610-1 version 0.0.4.

Key features

  • CAN FD
    • Supports Flexible Data Rate
  • CAN Formats
    • Supports STANDARD and EXTENDED CAN format
  • CAN Frames
    • Supports data, remote, error and overload frames
  • CAN XL
    • Supports XL extension of the protocol which fills the gap between CAN FD and Ethernet
    • Transceiver model is required as it is not part of the VIP model.
  • Configurable Agents
    • Supports multiple CAN agent instantiations
  • Error Frames
    • Supports generation of frames with errors in particular fields, such as CRC, delimiters, and EOF
  • Fault Confinement
    • Tracks error counters and fault states
  • ISO Conformance Test
    • Supports ISO 16485 conformance test regression suite
    • Support for Section 9 of ISO conformance test suite
  • Response for DATA Frames
    • Supports generation of DATA frames in response to a REMOTE frame with a particular ID

Block Diagram

Specifications

Identity

Part Number
Simulation VIP for CAN
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about CAN / CAN-FD / CAN-XL IP core

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

How a Multi-Protocol PHY Simplifies Physical AI Connectivity

Physical AI systems must move large amounts of data across two very different connectivity domains. Accelerators and local storage need high-bandwidth, low-latency links close to the compute SoC, while sensors and control modules require reliable connectivity across the larger platform. Supporting both domains with separate high-speed PHYs can increase silicon area and integration complexity.

Frequently asked questions about CAN / CAN FD / CAN XL IP cores

What is Simulation VIP for CAN?

Simulation VIP for CAN is a CAN / CAN-FD / CAN-XL IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this CAN / CAN-FD / CAN-XL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CAN / CAN-FD / CAN-XL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP