Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: SRAM

Silterra 0.18um ULL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via ROM Compiler

VeriSilicon SMSB 0.18um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor …

Silterra 180nm G Pre-Silicon View all specifications

Overview

VeriSilicon SMSB 0.18um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor Manufacturing Corporation (SMSB) 0.18um 1P6M Ultra Low Leakage 1.8V/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it has been optimized for area efficiency.

Key features

  • Low Leakage
  • Low Power
  • High Density
  • High Speed
  • Automatic Power Down
  • Tri-State Output(SRAM only)
  • Write Mask Function(SRAM & Register File)
  • More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp

Silicon Options

Foundry Node Process Maturity
Silterra 180nm G Pre-Silicon

Specifications

Identity

Part Number
SMSB18ULL
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.

Provider

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Frequently asked questions about SRAM IP cores

What is Silterra 0.18um ULL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via ROM Compiler?

Silterra 0.18um ULL Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Via ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for silterra Pre-Silicon.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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