112G LR-Max Ethernet PHY for TSMC N5
Synopsys, Inc.
•
HQ:
USA
Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networki…
- TSMC
- 5nm
- N5FF
Compare 244 CXL IP Listing from 22 vendors
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AES-GCM Ultra-low latency crypto engine
Secure-IC• HQ: FranceThe AES-GCM Ultra-low latency crypto engine is targeted for CXL link encryption with an implementation of the AES-GCM algorithm c…
- AES
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PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
Synopsys, Inc.• HQ: USAThe multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to mee…
- PCIe Gen5
- TSMC
- 16nm
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Verification IP for Universal Chiplet Interconnect Express (UCIe) up to 3.0
Synopsys, Inc.• HQ: USASpecifications: UCIe v1.0, v1.1, v2.0, v3.0 Interfaces: FDI/RDI/PHY link DUT Types/Topology D2D Adapter, Phy, Protocol, Full Stac…
- Verification IP
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Panmnesia• HQ: Korea
Comprehensive Portfolio of Device-Specific PCIe 7.0-CXL 4.0 IP
- CXL
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UCIe D2D Adapter & PHY Integrated IP
Chip Interfaces ApS• HQ: DenmarkA UCIe solution ready to support any protocol layer The D2D Adapter for UCIe combined with the UCIe PHY from a UCIe solution read…
- UCIe
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Qbit labs• HQ: USA
PCIe Gen 6 Phy
- Multi-Protocol PHY
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Universal Chiplet Interconnect Express(UCIe) VIP
MAXVY Technologies Pvt Ltd• HQ: IndiaThe UCIe VIP , a solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of y…
- Verification IP
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Chip Interfaces ApS• HQ: Denmark
Industry , Silicon Proven, 32 Gbps per pin, backed by a portfolio of verification tools, PHY interoperability and integration.
- UCIe
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Cadence Design Systems, Inc.• HQ: USA
Used by all PCIe, IP, and SoC design verification teams for all generations.The Cadence® Verification IP (VIP) for PCI Express® (…
- Verification IP
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CrossFire Technologies• HQ: USA
An optimum deployment of DCI in a Chipletized system would implement full DCI interfaces on all Chiplets.
- Custom
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UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys, Inc.• HQ: USASynopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
- TSMC
- 3nm
- N3P
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UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys, Inc.• HQ: USASynopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
- TSMC
- 5nm
- N5A
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UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys, Inc.• HQ: USASynopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
- UCIe
- Available on request
- Available
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UCIe-A PHY for Advanced Package (x64) in TSMC (N5)
Synopsys, Inc.• HQ: USASynopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
- UCIe
- Contact the Vendor
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UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
Synopsys, Inc.• HQ: USASynopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
- UCIe
- Available on request
- Available
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Panmnesia• HQ: Korea
Two-Digit Nanosecond PCIe 7.0-CXL 4.0 Link Controller IP
- Controller
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Neoverse Compute Subsystems N3 (CSS N3)
Arm Ltd.• HQ: Great BritainThe Performance-per-Watt Arm Neoverse N3 Platform Validated by Arm for Networking and Edge Markets configurable to target 5G, DPU…
- CPU
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Neoverse Compute Subsystems V3 (CSS V3)
Arm Ltd.• HQ: Great BritainThe High-Performance Arm V3 Platform Performance-Optimized and Validated by Arm Arm Neoverse CSS V3 is the fastest path to buildi…
- CPU
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UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
Synopsys, Inc.• HQ: USASynopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
- TSMC
- 6nm
- N6