PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
- PCIe Gen5
PCIe 5.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
UCIe-S PHY for Standard Package (x16) in TSMC N3E, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
PCIe 6.0 PHY, TSMC N5 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®) 6.x meets today’s demands for higher bandwidth and power efficiency across netw…
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC N3P, North/South Orientation
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hypers…
PCIe 6.0 PHY, SS SF2A x4 1.2V, N/S for Automotive, ASIL B Random, AEC-Q100 Grade 2
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency ac…
Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfa…
Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7 Av…
The PCIe Switch Verification IP provides an effective & efficient way to verify the components interfacing with the PCIe Switch i…
Neoverse Compute Subsystems N2 (CSS N2)
Neoverse CSS N2: The Arm Neoverse N2 Platform, Delivered to Partners as a Verified, Performance-Validated Customizable Subsystem …
PCIe 6.0 PHY G2 , SS SF4X x4, North/South (vertical) poly orientation
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency ac…
Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for …
SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most dem…
32G PHY in TSMC (N5A, N3A) for Automotive
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
32G PHY in Samsung (10nm, 8nm, 4nm, 5nm, SF2)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
32G PHY in TSMC (16nm, 12nm, N7, N6, N5, N5A, N3E. N3P)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
28G LR Ethernet PHY in GF (12nm)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
28G LR Ethernet PHY in TSMC (16nm, N7, N6)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
28G LR Ethernet PHY in Samsung (SF5A)
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
PCIe 5.0 PHY NCS in TSMC (N7, N6, N5)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to mee…