Vendor: iv-tec GmbH Category: Video Processing

Real Time Video Image rotation HD up to 1920x1080p60Hz

The IV-ROT IP implements a full rotation (0-360°) algorithm for high resolution images like HD (1920x1080p30/ 1920x1080p60).

Contact Provider Request Datasheet

Overview

The IV-ROT IP implements a full rotation (0-360°) algorithm for high resolution images like HD (1920x1080p30/ 1920x1080p60). The maximum resolution is 2048x2048.
The throughput of the design is 1 pixel per cycle on 3 components 8bit each (e.g. RGB or YUV444). The rotation process requires about 1 frame delay through external SDRAM/DDR. The picture content can be interlaced or progressive. De-interlacing is recommended (iv-deint)
Programmable parameters are:
- pictures size xy
- rotation base xy
- rotation angle Δω
- rotation size xy
Program parameters changes are applied during vertical blanking. The algorithm requires about 3 full frame storage. Rotation starts when one full picture is written to memory. Processed pixel are directly displayed.

Key features

  • Free programmable full
  • picture rotation (0-360°)
  • Resolution up to 2048x2048
  • 1pixel per clock throughput
  • Programmable Angle
  • inc-Omega = 0.022 °
  • Programmable Base
  • x/y = 1pix
  • Cropping option selectable
  • Padding options
  • Rotation Shape (Rectangular, others in 64x64 tiles)
  • Bandwidth efficient architecture
  • Low processing delay : ~1 Frame

Benefits

  • Real time rotation based on single register input value.
  • Zoom option available (up to 4x)

What’s Included?

  • Verilog 2001 compatible code
  • Customized for your application
  • Integrated to your existing code
  • Easily interfaced to standard I/O standards
  • Excellent code and expression coverage
  • FPGA proven design
  • Real time demos available
  • Application support available
  • HDL Source Licenses
    • Synthesizable Verilog 2001 RTL* (VHDL option available)
    • Self checking Verilog Testbench **
    • VCD dump option
    • Expected results generator
    • Simulation script
    • Test stimuli vectors
    • Test config vectors
    • Generic API optional available
    • Coverage reports
    • Synthesis script
    • IP Documentation
  • Netlist Licenses
    • For FPGA platforms: XILINX, Lattice, Altera
    • For ASIC: please ask

Specifications

Identity

Part Number
iv-rot
Vendor
iv-tec GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

iv-tec GmbH
HQ: Germany
Contact iv-tec GmbH

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is Real Time Video Image rotation HD up to 1920x1080p60Hz?

Real Time Video Image rotation HD up to 1920x1080p60Hz is a Video Processing IP core from iv-tec GmbH listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP