The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscill…
The lock detector monitors the current status of PLL by comparing the phase difference of VCO divided signal and reference oscillator signal with required value. It is available to set the lock monitoring period and the lock detector accuracy (5.5...12 ns).
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 180nm | BCDG2 | Silicon Proven |
Note: some files may require an NDA depending on provider policy.
PLL lock detector with low current consumption and high accuracy is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.