Vendor: Cologne Chip AG Category: PLL

Phase Locked Loop (PLL) Frequency Synthesizer Core

For general purpose Phase Locked Loops (PLL), ASIC designers have to rely on analog VCOs until today.

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Overview

For general purpose Phase Locked Loops (PLL), ASIC designers have to rely on analog VCOs until today. Now Cologne Chip has come up with a fully digital approach: C3-PLL-2, an IP core for frequency synthesizer applications.
C3-PLL-2 relies on the DIGICC design concept of Cologne Chip, which makes it possible to be easily implemented in all process technologies as a fully digital circuitry. The lock time of the PLL is very low while the used circuit area is smaller than that of competing technologies. Because of its pure digital nature the C3-PLL-2 does neither require any additional pad or pin nor external or internal loop capacitors. External filters for the supply voltage are normally not needed. A patent is pending for this innovation of Cologne Chip.

C3-PLL-2 is based on C3-PLL-1 and contains additional read/write registers with address decoder, a predivider and a post-scaler.

Key features

  • Fully digital - designed for use with standard cell libraries for digital logic
  • Implementable in any digital CMOS process technology
  • Typical oscillator frequency ranges:
    • 0.50 µm: 60-120 MHz
    • 0.35 µm: 100-200 MHz
    • 0.25 µm: 140-280 MHz
    • 0.18 µm: 160-320 MHz
    • 0.13 µm: 180-360 MHz
      • 90 nm: 200-400 MHz
    • Frequency multiplication range: 5 to 255
    • Predivider and post-scaler with divider range 1..256 each
    • Jitter similar to analog PLLs
    • No pads, special pins, external loop filter capacity or supply voltage filters needed
    • Very fast lock time (worst case 2,000 reference clocks)
    • Stand-by mode (oscillator stopped but center frequency preserved) >> super-fast lock time when returning from stand-by mode (only some clock cycles)
    • Stand-by also reduces power to zero (only leakage current)
    • Very small area (< 3,000 gates)

Benefits

  • Fully digital
  • Implementable in any digital CMOS process technology
  • No pads, special pins or external loop filter capacity or supply voltage filters needed

What’s Included?

  • Compiled netlist for destination technology and test vectors.

Specifications

Identity

Part Number
C3-PLL-2
Vendor
Cologne Chip AG
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Cologne Chip AG
HQ: Germany
Contact Cologne Chip AG

Learn more about PLL IP core

Fully Digital Implemented Phase Locked Loop

This paper shows an approach for a PLL that only uses digital cell libraries. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the PLL also can be used in a FPGA. One of the most astonishing feature is the possibility to check the whole functionality with a pure digital simulator. So without an analog simulator like Spice performance values like frequency and jitter can be checked.

Fully Digital Implemented Phase Locked Loop

This paper shows an approach for a PLL that only uses digital cell libraries. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the PLL also can be used in a FPGA. One of the most astonishing feature is the possibility to check the whole functionality with a pure digital simulator. So without an analog simulator like Spice performance values like frequency and jitter can be checked.

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Frequently asked questions about PLL IP cores

What is Phase Locked Loop (PLL) Frequency Synthesizer Core?

Phase Locked Loop (PLL) Frequency Synthesizer Core is a PLL IP core from Cologne Chip AG listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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