25MHz to 200MHz Low Jitter Low Power PLL
CT20900 is a PLL providing 33, 66, 50 and 200MHz clocks based on a 25MHz reference clock.
Overview
CT20900 is a PLL providing 33, 66, 50 and 200MHz clocks based on a 25MHz reference clock. It comprises a Phase Frequency Detector with internal charge pump that detects the phase difference between the 25MHz reference clock and the divided by 8 version of the 200MHz clock generated by the Voltage Controlled Oscillator (VCO).
The loop includes a second order Low Pass Filter (LPF)
Key features
- Fully Differential Topology
- Charge Pump 3rd order configuration
- 2nd order passive loop filter
- Fin = 25MHz, Fout = 33, 50, 66 and 200MHz
- Maximum Jitter < 50ps
- Max current consumption = 2.3mA
Block Diagram
Benefits
- Easy portability
Applications
- Automotive Ethernet
- Baseband Telecom
What’s Included?
- Datasheet
- Integration guidelines
- GDS2 and LVS Netlist
- Footprint (.LEF)
- Test Specifications
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about PLL IP core
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Frequently asked questions about PLL IP cores
What is 25MHz to 200MHz Low Jitter Low Power PLL?
25MHz to 200MHz Low Jitter Low Power PLL is a PLL IP core from Canova Tech Srl listed on Semi IP Hub.
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.