Vendor: T2M GmbH Category: Multi-Protocol PHY

PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC

The PCIe 2.0 PHY IP presents a configurable physical layer (PHY) IP solution tailored for Consumer Electronics.

UMC 28nm HPC In Production View all specifications

Overview

The PCIe 2.0 PHY IP presents a configurable physical layer (PHY) IP solution tailored for Consumer Electronics. It combines mixed signal circuits to facilitate data transfer speeds of both 2.5GT/s and 5.0GT/s, adhering to PCIe 2.0 basic standards. Comprising two layers, namely the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), it seamlessly interfaces with the PCIe 2.0 MAC layer through the standard PIPE-3.0 interface.

Designed for minimal power consumption and compact device footprint, the PCIe 2.0 PHY IP transceiver maintains excellent performance and data throughput. It incorporates an on-chip physical transceiver solution featuring ESD protection, an integrated self-test module with built-in jitter injection, and a dynamic equalization circuit ensuring comprehensive support for high-performance architectures.


The PCIe 2.0 PHY IP presents a configurable physical layer (PHY) IP solution tailored for Consumer Electronics. It combines mixed signal circuits to facilitate data transfer speeds of both 2.5GT/s and 5.0GT/s, adhering to PCIe 2.0 basic standards. Comprising two layers, namely the Physical Media Attachment (PMA) layer and the Physical Coding Sublayer (PCS), it seamlessly interfaces with the PCIe 2.0 MAC layer through the standard PIPE-3.0 interface.

Designed for minimal power consumption and compact device footprint, the PCIe 2.0 PHY IP transceiver maintains excellent performance and data throughput. It incorporates an on-chip physical transceiver solution featuring ESD protection, an integrated self-test module with built-in jitter injection, and a dynamic equalization circuit ensuring comprehensive support for high-performance architectures.

Key features

  • Compatible with PCIe base Specification
  • Full compatible with PIPE4.2 interface specification
  • Independent channel power down control
  • Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
  • Support 16-bit/32bit parallel interface
  • Support for PCIe gen1(2.5Gbps) and PCIe gen2(5.0Gbps)
  • Support flexible reference clock frequency
  • Support 100MHz differential reference clock input or output (with SSC optionally) in PCIe Mode
  • Support Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm
  • Support programmable transmit amplitude and Deemphasis
  • Support TX detect RX function in PCIe Mode
  • Support Beacon signal generation and detection in
  • Production test support is optimized through high coverage at-speed BIST and loopback
  • Integrated on-die termination resistors and IO Pads/Bumps
  • Embedded Primary & Secondary ESD Protection
  • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
  • Silicon Proven in UMC 28HPC+

Block Diagram

PCIe 2.0 Serdes PHY IP in 28HPC block diagram

What’s Included?

  • GDSII & layer map
  • Place-Route views (.LEF)
  • Liberty library (.lib)
  • Verilog behaviour model
  • Netlist & SDF timing
  • Layout guidelines, application notes
  • LVS/DRC verification reports

Silicon Options

Foundry Node Process Maturity
UMC 28nm HPC In Production

Specifications

Identity

Part Number
PCIe 2.0 Serdes PHY IP in 28HPC
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Multi-Protocol PHY IP core

Frequently asked questions about Multi-Protocol PHY IP cores

What is PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC?

PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC is a Multi-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for umc In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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