Learn more about Protocol Bridge IP core
Developing and verifying a control network in a low-power SoC is a challenging task, especially managing the different states of regulators and modes of power domains.
This article first describes state-of-the-art approaches to addressing this issue, and then delves into the solution promoted by Dolphin Integration to go further, thanks to the easy and secure Maestro� solution to manage SoC power mode transitions.
Understand the role of the UCIe D2D Adapter in enabling reliable, scalable, multi-protocol die-to-die communication for chiplet architectures.
Script/simulation approach speeds SoC verification
This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures
Synthesizable verification IP speeds design cycle
Synthesizable Verification IP