Amplifier linearization promotes efficiency in multi-carrier WCDMA basestation
Amplifier linearization promotes efficiency in multi-carrier WCDMA basestation
Vendor:
NTLab
Category:
Amplifier
Multiplexer - amplifier
The cell is combined into one block multiplexer and amplifier.
Overview
The cell is combined into one block multiplexer and amplifier. The multiplexer selects one of the required inputs by a combination of control signals and transmits the amplified signal to the output.
Temperature compensation mode is used to compensate gain vs. environment temperature.
The block is fabricated on SMIC CMOS 0.18 um technology.
Key features
- SMIC CMOS 0.18 um
- Input and output matching 50 Ohm
- No external matching components required
- Built-in adjustment of matching
- Gain temperature compensation mode
- Adjusted gain
- Portable to other technologies (upon request)
Block Diagram
180SMIC_MUX_02 block diagram
Applications
- Navigation receiver
What’s Included?
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- GDSII
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Documentation
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 180nm | G | Silicon Proven |
Specifications
Identity
Part Number
180SMIC_MUX_02
Vendor
NTLab
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Lithuania
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Frequently asked questions about Amplifier IP cores
What is Multiplexer - amplifier?
Multiplexer - amplifier is a Amplifier IP core from NTLab listed on Semi IP Hub. It is listed with support for smic Silicon Proven.
How should engineers evaluate this Amplifier?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Amplifier IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.