Vendor:
Mikroprojekt
Category:
Display Controller
Multilayer Configurable Display Controller
The IQ-DispML is a multi-layer, fully software configurable display controller IP core.
Overview
The IQ-DispML is a multi-layer, fully software configurable display controller IP core. It performs continuous refresh of graphical flat panel displays (TFT LCD, AMOLED) from the designated frame buffers located in a memory device mapped to the system bus.
Multiple layers are blended into a single image, which is outputted to the display. SDRAM and SRAM devices are supported as frame buffers, depending on the bandwidth requirements.
IQ-DispML is designed to provide an optimum tradeoff of performance and resource utilization in FPGA devices while retaining a high degree of configurability. The IP core can be additionally scaled down at compile time by reducing the number of layers, bus widths and fixing timing parameters, allowing the user to fully optimize the IQ-DispML for a specific configuration.
Multiple layers are blended into a single image, which is outputted to the display. SDRAM and SRAM devices are supported as frame buffers, depending on the bandwidth requirements.
IQ-DispML is designed to provide an optimum tradeoff of performance and resource utilization in FPGA devices while retaining a high degree of configurability. The IP core can be additionally scaled down at compile time by reducing the number of layers, bus widths and fixing timing parameters, allowing the user to fully optimize the IQ-DispML for a specific configuration.
Key features
- Fully programmable clock and timing control for flat panel displays with progressive scanning
- Support for resolutions up to 4096x4096
- Completely variable timing parameters, for standard or specific display resolutions
- Support for 8,16, 18 or 24 bit RGB output color depth
- Standard or multiplexed display data bus
- Display power control lines
- Interrupt generation on vertical sync for software synchronization
- Frame buffer management Double buffering to reduce image flicker
- Variable frame buffer organization with software-configurable memory stripe
- Image scroll via unconstrained frame buffer addressing
- Frame buffer color depth support
- Alpha blending of all layers, with per-layer additional transparency (“layer fading”)
- Independent positioning and dimensioning of all layers
- Compile-time configuration for reducing resource cost by fixing parameters
- Support for multiple clock domains to ease timing closure
- Integrated DMA memory master supporting low-overhead burst transfers
- Configuration bus slave interface with address-mapped registers
Block Diagram
IQ-DispML block diagram
Applications
- Vending machines
- Video monitors
- Automotive infotainment
- Medical instrumentation
- Human machine interface (HMI) systems
- Mobile devices
Specifications
Identity
Part Number
IQ-DispML
Vendor
Mikroprojekt
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Croatia
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Frequently asked questions about Display Controller IP
What is Multilayer Configurable Display Controller?
Multilayer Configurable Display Controller is a Display Controller IP core from Mikroprojekt listed on Semi IP Hub.
How should engineers evaluate this Display Controller?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Display Controller IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.