Compatible with JEDEC standards LPDDR4X , LPDDR5 and LPDDR5X SDRAMs; Supports for data transfer rate up to 8533Mbps
- Controller + PHY + 1
- LPDDR5X
LPDDR Interface IP cores provide the controller, PHY, and training technologies required to connect SoCs and ASICs to low-power DRAM, enabling high memory bandwidth while minimizing energy consumption in power-sensitive applications.
This category includes IP solutions supporting LPDDR4, LPDDR5, LPDDR5X, and LPDDR6 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, initialization and training engines, power management features, ECC capabilities, and advanced signal integrity technologies optimized for mobile, AI, automotive, and edge computing platforms.
Compatible with JEDEC standards LPDDR4X , LPDDR5 and LPDDR5X SDRAMs; Supports for data transfer rate up to 8533Mbps
LPDDR5X Memory Model provides an smart way to verify the LPDDR5X component of a SOC or a ASIC.
LPDDR5X Synthesizable Transactor
LPDDR5X Synthesizable Transactor provides a smart way to verify the LPDDR5X component of a SOC or a ASIC in Emulator or FPGA plat…
LPDDR5X is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5X draft JEDEC specification, JESD209-5B specif…
LPDDR5X Assertion IP provides an efficient and smart way to verify the LPDDR5X designs quickly without a testbench.
Our LPDDR5X PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of m…
LPDDR5X Secondary/Slave (memory side!) PHY
This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products.
LPDDR Controller supporting LPDDR5X, LPDDR5, and LPDDR4X
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR5T / LPDDR5X / LPDDR5 Controller
The LPDDR5 Controller supporting LPDDR5T, LPDDR5X, LPDDR5 controller core is designed for use in applications requiring high memo…
LPDDR Controller ASIL B Compliant supporting LPDDR5X, LPDDR5 and LPDDR4X for Automotive Applications
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Secure Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR5X/5/4X PHY in Samsung (SF4X)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) an…
LPDDR5X/5/4X PHY in TSMC (N5, N4P, N3E)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) an…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 PHY V2 - TSMC N5A for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…