Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
Xenergic Ab
Category:
SRAM
Memory Compiler
Key features
- 70-90% power reduction
- Unmatched performance
- Multi-technology support
- Tailored for design needs
- Smooth & flexible configuration
- Fast delivery
- No compromise on area
Block Diagram
MemoryTailor block diagram
Specifications
Identity
Part Number
MemoryTailor
Vendor
Xenergic Ab
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Sweden
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Frequently asked questions about SRAM IP cores
What is Memory Compiler?
Memory Compiler is a SRAM IP core from Xenergic Ab listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.