Overview
The LPDDR2/3_DDR3/4 library includes the combo driver/receiver cells with embedded power cells, the driver impedance calibration cell, and a full complement of support cells for both single-ended and differential signaling for LPDDR2, LPDDR3, DDR3, DDR3L, DDR3U, and DDR4 applications. Also included is a full complement of power, corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Learn more about High-Speed IP core
With the rapid growth of AR/VR and high-resolution imaging systems such as drones and action cameras, MIPI CSI (Camera Serial Interface) and MIPI DSI (Display Serial Interface) require both high data throughput and low power consumption. M31 provides a MIPI C-PHY and D-PHY IP combo solution implemented on TSMC N3P and N3C processes.
Today, High-Speed SerDes serves as the foundation of industry standards such as PCIe, Ethernet, USB, and UCIe, making it a critical technology for modern semiconductor systems. As the industry progresses towards higher data rates and increasingly complex architectures, SerDes continues to play a central role in enabling reliable and scalable connectivity, especially at lower nodes.
This post provides an in-depth look at the fundamentals of high-speed interconnects, AI/HPC trends (HBM/D2D/CPO), and the three critical requirements of Physical AI: Deterministic Latency, Functional Safety (ISO 26262), and Automotive Reliability (AEC-Q100).
Innosilicon, a leading IP provider, offers a complete PCIe 5.0 solution stack that includes both PHY and controller IPs. Although both layers are crucial to achieving a fully compliant and high-performance PCIe interface, this paper deep dives into the technical challenges of PHY design, highlighting insights drawn from real-world design margins, receiver robustness, and advanced jitter analysis in the context of Gen5 systems.
LTTPR support is quickly becoming a cornerstone of next-gen DisplayPort architectures, particularly in automotive, industrial, and multi-display environments. Here's what you need to know.
Protocol standards and speeds are advancing rapidly to boost productivity and efficiency for high-performance computing (HPC), AI training, and other applications, with the arrival of PCI Express (PCIe) 7.0 being the latest example.
